The present invention relates generally to integrated circuits, and more particularly, to self-planarizing layers formed on an integrated circuit.
During mass production of integrated circuits, a number of well defined regions of a semiconductor wafer become individual, yet circuits normally involves forming one or more layers over the semiconductor wafer, and then patterning these layers. Since the desired integrated circuits are identical, fabrication is made efficient by forming these layers over the entire semiconductor wafer and then performing subsequent processing steps simultaneously to each integrated circuit. These processes are often repeated until all the elements necessary are formed on each integrated circuit.
Wafer etching is a processing step used at many points in mass production of integrated circuits. The general term etching is used to describe techniques by which material can be removed from layers formed over a semiconductor wafer. The etching process, in conjunction with masking and cleaning processes, is often used to pattern layers of a semiconductor wafer.
As is well known to those of skill in the art, etching is typically divided into two categories; wet etching and dry etching. Dry etching, rapidly becoming the most popular etching method within the industry, involves removal of material by momentum transfer from ion bombardment, subjection of the wafer to a reactive chemical species, or a combination of the two. The dry etch process which combines both methods is known as reactive ion etching. In reactive ion etching, the semiconductor wafer is exposed to a plasma and a bias voltage is forced on the wafer to accelerate ions present in the plasma towards the wafer. The plasma is typically formed from an inert gas and the chemically reactive species.
FIG. 1 illustrates a prior art reactive ion etcher 10. The reactive ion etcher 10 includes etchant chemical plumbing 12 and control valves 14, coolant plumbing 16 and a corresponding control valve 18, a radio frequency (rf) generator 20, and a housing chamber 22. A showerhead 24 and chuck 26 are both internal to the chamber 22. Typically a semiconductor wafer 28 is mounted on the chuck 26. Additionally, the walls of the chamber 22 and either the chuck 26 or the showerhead 24 are electrically coupled to ground. When operating, the rf generator 20 creates a positive charge (hence creating an anode) on the larger electrode and a negative charge (hence creating a cathode) on the smaller electrode. As should be apparent, the electrode which is attached to the walls of the chamber 22 (either the chuck 26 or the showerhead 24) is the electrode of large area.
The etching process often includes a non-powered step and a powered step. In the non-powered step, the chamber 22 is filled with etchant chemicals according to a specific etch recipe while the rf generator 20 is off. Once the chamber 22 is prepared, the rf generator 20 is turned on and then causes oscillations in the plasma cloud 30 creating ions and free electrons. The positive ions accelerate towards the cathode 26, thereby anisotropically etching the surface layers of the wafer 28.
During etching, the temperature of the semiconductor wafer 28 rises due to exposure to the plasma 22. In order to prevent overheating and maintain control of the etching process, a small amount of gaseous helium coolant is bled underneath the wafer 28 by way of the coolant chemical plumbing 16 and the corresponding valve 18. By way of explanation, the temperature of the wafer 28 may directly effect many of the etch parameters such as etch rate, undercut, and selectivity. Therefore it is desirable to control this temperature.
Prior art etch recipes include carbon chemicals, such as CHF.sub.3 and C.sub.2 F.sub.6. As is well know to those skilled in the art, etching processes which use reactive chemicals high in carbon are "dirty". Because of carbon residue left by such high carbon chemicals, maintenance tasks such as cleaning the etching chamber must be performed regularly in order for the chamber to function properly. This results in costly downtime for critical machinery.
As will be appreciated by those skilled in the art, reactive ion etching is primarily an anisotropic etching method. That is, reactive ion etching removes material in primarily one direction, as opposed to removing material uniformly in all directions.
FIG. 2 shows a cross-sectional view of a prior art integrated circuit structure 40 which was fabricated in part by a prior art recipe using CHF.sub.3 and C.sub.2 F.sub.6. The integrated circuit structure 40 includes a semiconductor substrate 42, an island 43 comprised of a conductive layer 44 and an oxide layer 46, an inter-level dielectric (ILD) layer 48, and a spin-on glass (SOG) layer 50. While only one island 43 is shown in FIG. 2, typically the integrated circuit structure 40 has a plurality of islands 43, and the integrated circuit structure 40 is one of a plurality of integrated circuit structures formed on a single semiconductor wafer. The islands 43 are preferably formed by standard photolithography patterning processes.
Typical prior art etch recipes create a plurality of islands 43 formed from portions of the oxide layer 44 and the conductive layer 46, with each layer of a particular island 43 having lateral dimensions which are substantially the same. Hence, the sidewall profile of each island 43 is vertical. Note that FIG. 2 shows only a two-dimensional cross-sectional view of the island wherein the lateral dimensions of the conductive layer 44 and the oxide layer 46 are substantially the same. In actuality, the integrated circuit structure 40 has a depth dimension (i.e. the dimension which is perpendicular to the page), and the depth of each layer would also be substantially the same.
After the islands 43 are formed, two layers, an ILD layer 48 and a SOG layer 50 are applied over the oxide layer 46 where the ILD layer 48 is for insulation purposes and the SOG layer 50 serves to planarize the surface of the wafer for subsequent processing steps. In some cases a boron phosphate silicate glass (BPSG) planarizing layer may be used in lieu of the SOG layer 50. In either case, once the ILD layer 48 and the SOG layer 50 (or BPSG layer) have been formed, the integrated circuit structure 40 typically undergoes additional fabrication steps. Often additional layers are formed and are in turn patterned. In order to perform these subsequent steps, the upper surface 52 of the SOG layer 50 must be substantially planar. However, as can be seen from FIG. 2, the topography of the upper surface 52 is not substantially planar, rather it is especially "bumpy" in the area over the island 43. Consequently, a planarizing step such as polishing might have to be performed in order to form a planar upper surface 52 on the SOG layer 50. These additional processing steps are expensive and time consuming, and may result in reduced yield of functional integrated circuits.